Serial Data Line Transmission Project


This serial data interface works well, but the current design has limited use in the field.

1. Introduction

This report describes the design of a one way serial data interface with one data line, one control line, and two power lines. This circuit is physically split in to two parts: a transmitter and a receiver, as is described below.

Circuit Design Rationale

Transmission Protocol

The protocol that was designed for the data transmission in this setup is, in the interests of ease of implementation, very simple. It has no limit on the number of bits that can be transferred, it has no inherent dependence on the speed of transmission (that is to say that the limit is set by the speed at which ICs can read the data), and does not require any special timing on the part of either the receiver or the transmitter.

However, the protocol used is unable to signal the start or end of transmission, so a decision must first be made concerning the size of each word transmitted. In this particular design, each word will consist of 4 bits, allowing 16 distinct possible states that can be transmitted.

The protocol uses two lines, called the Data Line and Control Line. For each bit of data, the Data Line is set to the value of the next bit. The Control Line is then flashed. Whether the control line is flashed 0-1-0 or 1-0-1 is unimportant, so long as the transmitter keeps this constant. In this implementation, the flash used was 0-1-0, and data was read by the receiver on the negative edge (1-0).

Circuit Design

There are five quite distinct parts to this circuit, each centred around a chip. They are:

  1. User Interface
  2. Transmission Clock
  3. Transmit Buffer
  4. Receive Buffer
  5. LEDs

Each will now be discussed separately.

User Interface

This part of the circuit consists of two two-state switches and one push switch. It provides three essential inputs to the rest of the circuit: the Data Set Trigger, the Transmit Trigger, and User Data.

The User Data and Data Set Trigger lines are used to set the data in the Transmit Buffer prior to transmission.

The Transmit Trigger is used to begin transmission of the data from the Transmit Buffer to the Receive Buffer.


The user sees two two-state switches and one push switch. The first two-state switch selects the effect of the push switch. The possibilities are Data Set Mode and Data Transmit Mode.

In Data Set Mode, the second two-state switch decides the value of the next bit which is to be shifted into the Transmit Buffer (i.e., it sets the value of the User Data line). The push switch, which has to be debounced to make it reliable, actually triggers the shift, by controlling the Data Set Trigger line.

In Data Transmit Mode, the second two-state switch plays no role and the debounced push switch actually triggers the start of the data transfer, by controlling the Transmit Trigger line.


This section of the circuit uses no logical inputs from other parts of the circuit. It only uses the three inputs from the user.


This part of the circuit provides three data lines to the rest of the circuit: Data Set Trigger (used by the Transmission Clock), and User Data and the Transmit Trigger (used by the Transmission Clock).


The only real logic in this circuit module is the latch used to debounce the trigger switch.

Transmission Clock

The Transmission Clock is the synchronisation part of the circuit. It controls the transfer of data by waiting for a signal to begin and then generating four 0-1-0 pulses.


There are two inputs to the Transmission Clock circuit: a clock input and the Transmit Trigger line.

The clock input must be continuously toggling between 0V and 5V (logic 0 and logic 1). In practice, it does not matter if the clock input is regular or not, since the circuit gets its notion of time directly from this input. In this implementation, a function generator was used, and frequencies up to the top 10MHz were used successfully with no noted anomalies in transmission. Higher frequencies could probably have been used, but were not tried.

The Transmit Trigger line should be lowered (1-0) to trigger the start of four flashes on the main output (see below).


The Transmission Clock circuit has two outputs, the MSB (Most Significant Bit) and LSB (Least Significant Bit). The LSB is the main Transmission Clock output. It will flash four times once the Transmission Clock circuit's Transmit Trigger input is lowered.

The MSB is merely an interface signal, which is connected to an LED. When this signal is low (0), then transmission is taking place. When it is high (1), then the system is waiting either for the data to be changed or for transmission to be started.


The logic ensures that (a) the count will only start when the push switch is pressed (and Transmit Trigger goes low), (b) transmission cannot start if it is already occurring, and (c) transmission starts when the clock input clocks.

It also ensures that when the MSB goes high (and four bits have been sent) the clock input to the 74LS193 counter stops changing, and thus the LSB counter no longer flashes.

Transmit Buffer

This section of the circuit holds the four bits of data in a 74LS95B shift register. The data is set using the User Data and Data Set Trigger lines from the User Interface section. Also, when transmitting, the data is rotated around the shift register so that each bit is transmitted in turn.


As mentioned above, the three inputs are the User Data and Data Set Trigger lines from the User Interface section, and the LSB line from the Transmission Clock to rotate the shift register during transmission.


There are five outputs from this part of the circuit. The main four are quite simply the four data lines, QA1, QB1, QC1, and QD1. The QD1 output is used as the Data Line for transmission, and all four of these outputs are connected to a bank of LEDs that indicate the current state of the Transmit Buffer.

The fifth is merely a monitoring output for diagnosis purposes, and is detailed in the logic section, below.


The logic around the Transmit Buffer is the most complicated part of the circuit, although it is quite simple, involving only four gates. The complexity comes from having to cope with two distinct modes of operation, Data Set Mode and Data Transmit Mode.

The shift register IC has two inputs of importance here. The first is the Serial Clock. The Serial Clock is the output of an OR gate, ORing the LSB (used as the clock in Data Transmit Mode) and the Data Set Trigger (used as the clock in Data Set Mode). No protection has been wired in to prevent the two clocks from being used concurrently, but since the circuit is designed to be used with the transmission taking a ridiculously small amount of time, this is not important: the user could not feasibly switch to Data Transmit Mode, trigger the transmission, then switch to Data Set Mode and start setting the data before transmission being over.

The second input to the IC that is of importance here is the Serial Data In input. It controls what data is to be stored as the Most Significant Bit (QA1) in the IC when it is next rotated by clocking the Serial Clock input.

In Data Set Mode, the data is set by the User Data line (see the User Interface section). In Data Transmit Mode, the data is the Least Significant Bit (QD1), since the data is to be kept as it is transmitted.

In both cases, the data input is ANDed with the respective clock input to prevent the two data inputs from colliding, and the two AND gates' outputs are then ORed together to get the data for the Serial Data In input.

Receive Buffer

This is possibly the simplest part of the circuit. It is merely a shift register to receive the data from the Transmit Buffer as the Transmission Clock flashes its output.


There are two inputs, the Data Line, which comes from QD1 in the Transmit Buffer, and the Control Line, which comes from the LSB in the Transmission Clock section.


The Receive Buffer has six outputs, one for each bit of the shift register (namely, QA2, QB2, QC2, and QD2), and one for each of the inputs (Data Line and Control Line). All six connect to LEDs (see the next section).


The Data Line is wired into the Serial Data In input of the shift register. The Control Line is wired into the Serial Clock input of the shift register. That is all there is to it, really.


There are two types of LED circuits used in this design. The first is illuminated when the signal is high, and the second is illuminated when the power is low.


There are 13 different LEDs, and each has its own input. The things that are monitored on the transmission side are:

  1. User Data (indicating what is about to be shifted into the Transmit Buffer)
  2. Serial Clock of the Transmit Buffer (indicating when the Transmit Buffer is clocked)
  3. MSB of the Transmission Clock (which indicates when transmission is occuring)
  4. QA1
  5. QB1
  6. QC1
  7. QD1

And the things that are monitored on the receiving side are:

  1. Data Line
  2. Control Line
  3. QA1
  4. QB1
  5. QC1
  6. QD1


Well, obviously, 13 LEDs. No logic outputs arise from this section.


For all but the MSB LED, the circuit is simply input goes to 330W resistor, goes to LED, goes to NOT gate, goes to logic 1.

In the case of the MSB LED (indicating when transmission is in progress), the the NOT gate is not needed as the LED must light when the logic is low.

4. Discussion

The circuit worked very well. One major difficulty was that the sheer amount of wire involved (several meters in total) resulted in a circuit very sensitive to noise on the mains. For example, the circuit would drop to an undefined state when someone turned on a scope.

This could have been avoided by using the twisted pair technique of raising the transmitted data lines to some distance above 0V, and checking for slight voltage differences rather than an absolute voltage. This, however, was deemed outside the scope of this session.

The protocol could also do with some improvement, in particular in indicating when the transmission is to start or when it has ended. Some sort of parity bit for primitive error checking would be useful (or alternatively, a full scale CRC (cyclic redundancy check) or checksum system could be used). However, so long as the initial state is well defined and so long as transmission is perfectly reliable, the current protocol works fine.

5. Conclusion

This system works. It has minor flaws, which would have been solved had the time been available.

There are, however, serious architectural difficulties in the design (namely the start/stop and error correction problems). To make the system more resilient and easier to use (rather than easier to implement), the basis of the design would need rethinking.

Attached Documents

A hand drawn timing diagram of the Transmission Clock output and a hand drawn circuit schematic diagram have been included.


No other documents were referred to in the preparation of this report, with the exception of notes made during the design process, which are recorded in the author's Lab Book.